Biography
Research Topics
Research Summary
Publication
Experience


 

Prof. An-Yeu (Andy) Wu, IEEE Fellow, Distinguished Professor,Board of Governor Member in IEEE CASS

Department of Electrical Engineering & Graduate Institute of Electronics Engineering

National Taiwan University

BL-417, Department of Electrical Engineering, No.1, Sec.4, Roosevelt Road, Taipei 106, Taiwan

- Board of Governor (BoG) Member (2016-2018), IEEE Circuits and Systems Society (CASS). Tel: +886-2-3366-3641
Fax: +886-2-2365-6337

Email︰andywu@ntu.edu.tw
Web ︰http://access.ee.ntu.edu.tw

 

Index


Biography

An-Yeu (Andy) Wu (IEEE M’96-SM’12-F’15) received the B.S. degree from National Taiwan University in 1987, and the M.S. and Ph.D. degrees from the University of Maryland, College Park in 1992 and 1995, respectively, all in Electrical Engineering.

From August 1995 to July 1996, he was a Member of Technical Staff (MTS) at AT&T Bell Laboratories, Murray Hill, NJ, working on high-speed transmission IC designs. From 1996 to July 2000, he was with the Electrical Engineering Department of National Central University, Taiwan. In August 2000, he joined the faculty of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), where he is currently a Professor. His research interests include low-power/high-performance VLSI architectures for DSP and communication applications, adaptive/multirate signal processing, reconfigurable broadband access systems and architectures, bio-medical signal processing, and System-on-Chip (SoC)/Network-on-Chip (NoC) platform for software/hardware co-design. He has published more than 190 refereed journal and conference papers in above research areas, together with five book chapters and 16 granted US patents.

Dr. Wu is now serving as a Senior Editorial Board member of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), and an Associate Editor for JOURNAL of SIGNAL PROCESSING SYSTEMS (JSPS). He had served as Associate Editor for many leading IEEE journals in circuits and signal processing areas, such as the IEEE TRANSACTIONS ON SIGNAL PROCESSING, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II, and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He acted as the Lead Guest Editor of the special issue of “2010 IEEE Workshop on Signal Processing Systems (SiPS) in JSPS (published in Nov. 2011), and the special issue of “Signal Processing for Broadband Access Systems: Techniques and Implementations,” in EURASIP Journal on Applied Signal Processing (published in December 2003). He also acted as the Guest Editor of a special issue of “Low-Power, Reliable, and Secure Solutions for Realization of Internet of Things,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (published in March 2013). He also served on the technical program committees of many major IEEE International Conferences, such as ISCAS, ICASSP, SiPS A-SSCC, AP-ASIC, SOCC, and ISPACS. Prof. Wu served as the General Co-Chair of 2013 International Symposium on VLSI Design, Automation& Test (VLSI-DAT), and 2013 IEEE Workshop on Signal Processing Systems (SiPS). He also served as Technical Program Co-Chair of 2014 International SoC Design Conference (ISOCC) and 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). From 2012 to 2014, he served as the Chair of VLSI Systems and Applications (VSA) Technical Committee (TC), one of the largest TCs in IEEE Circuits and Systems (CAS) Society. He is now serving as a Board of Governor (BoG) Member of IEEE Circuits and Systems Society (CASS).

From August 2007 to Dec. 2009, he was on leave from NTU and served as the Deputy General Director of SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, TAIWAN, supervising WiMAX, Parallel Core Architecture (PAC) VLIW DSP Processor, and Android-based Multicore SoC platform projects. Meanwhile, he served as General Director of Semiconductor Industry Promotion Office (SIPO), under Ministry of Economy Affairs (MOEA), promoting semiconductor industry issues for the government. Since March 2014, Dr. Wu is in charge of the overall talent cultivation program in National Program for Intelligent Electronics (NPIE), under sponsorship of Ministry of Education in Taiwan.

Dr. Wu received numerous awards for his technical achievements and academic society services, including 2016 Technology Invention Award by Far Eastern Y.Z. Hsu Science and Technology Memorial Foundation; 2010 Outstanding EE Professor Award from The Chinese Institute of Electrical Engineering (CIEE), Taiwan, two Best Paper Awards in 2014 and 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Excellent Patent Award from Industrial Technology Research Institute (ITRI) in 2009, Teaching Award of Common Education Course, National Taiwan University in 2007, Dr. Wu Ta-you Award (Young Investigator Award) from National Science Council (NSC), Taiwan (the only nominee from Microelectronics research group of the NSC) in 2005, Distinguished Young Engineer Award from The Chinese Institute of Electrical Engineering (CIEE) in 2004, Best Engineering Paper Award, from the Chinese Institute of Engineers (CIE), Taiwan in 2004, and Young Chair Professor Award from Macronix International Corporation (MXIC) Education Foundation in 2003.

In 2015, Prof. Wu was elevated to IEEE Fellow for his contributions to “DSP algorithms and VLSI designs for communication IC/SoC.” Starting from August 2016, he serves as the Director of Graduate Institute of Electronics Engineering (GIEE), National Taiwan University.

(Index)

 
 

Service

Technical Committee

  • TC Chair (2012-2015) and Secretary & Chair-Elect (2009-2012), VLSI Systems and Applications (VSA-TC), IEEE Circuits and Systems Society (since 2002)
  • Design and Implementation of Signal Processing Systems (DISPS-TC), IEEE Signal Processing Society (since 2004)
  • Circuits and Systems for Communications (CASCOM) TC, IEEE CAS Society (since 2005)

Senior Editorial Board

  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)

Associate Editors

  • IEEE TRANSACTIONS ON SIGNAL PROCESSING
  • Journal of Signal Processing Systems (JSPS)
  • IEEE TRANSACTIONS ON SIGNAL PROCESSING
  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I
  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II
  • IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
  • EURASIP JOURNAL OF APPLIED SIGNAL PROCESSING, 2001-2004
  • JOURNAL of SIGNAL PROCESSING SYSTEMS (JSPS)

Guest Editorials

  • Special issue of “Low-Power, Reliable, and Secure Solutions for Realization of Internet of Things,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)(with Yen-Kuang Chen, Magdy A. Bayoumi, and Farinaz Koushanfar), to be published in 2013.
  • (Lead Guest Editor) Special issue of “2010 IEEE Workshop on Signal Processing Systems (SiPS) in Journal of Signal Processing Systems (JSPS), published in Nov. 2011.
  • Special Issue on “Networks-on-Chip: Architectures, Design Methodologies, and Case Studies” in Journal of Electrical and Computer Engineering (JECE) (with Sao-Jie Chen and Jiang Xu), published in Nov. 2012.
  • (Lead Guest Editor) Special issue on “Signal Processing for Broadband Access Systems: Techniques and Implementations” of EURASIP Journal of Applied Signal Processing (with Ut-Va Koc, Prof. Keshab Parhi, Sergios Theodoridis), published in Dec. 2003.

TPC

  • IEEE International Symposium on Circuits and Systems (ISCAS)
  • International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
  • IEEE Workshop on Signal Processing Systems (SiPS)
  • Asian Solid-State Circuit Conference (A-SSCC)
  • IEEE Asia-Pacific Conference on ASICs (AP-ASIC)
  • IEEE international SoC Conference (SOCC)
  • EEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

Honors and Awards

  • Technology Invention Award in “Communication Technology” area by Far Eastern Y.Z. Hsu Science and Technology Memorial Foundation, 2016.
  • Best Student Paper Award 2015 IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2015.
  • Best Paper Award 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2014.
  • 2010 Outstanding EE Professor Award from the Chinese Institute of Electrical Engineering (CIEE), Taiwan.
  • Best Paper Award, 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2010.
  • 2009 Excellent Patent Award, Industrial Technology Research Institute (ITRI), Taiwan (US Patent: 6,697,424)
  • 2007 Teaching Award of Common Education Course, National Taiwan University, Taiwan
  • 2005 Dr. Wu Ta-you Award (Young Investigator Award) from National Science Council (NSC), Taiwan (The only nominee from Microelectronics research group of the NSC.)
  • 2005 President Fu Si-nien Award, from National Taiwan University, for contributions in publications of SCI-rated journal papers
  • 2004 Distinguished Young Engineer Award from The Chinese Institute of Electrical Engineering (CIEE), Taiwan.
  • 2004 Best Engineering Paper Award, from the Chinese Institute of Engineers (CIE), Taiwan
  • 2003 Young Chair Professor Award from Macronix International Corporation (MXIC) Education Foundation
  • 1997~2000 Four times A-class Research Award, National Science Council, Taiwan
  • 2000 Teaching Material Award for the development of “Programmable DSP Laboratories”, Ministry of Education, Taiwan.
  • Advisor for more than 40 Thesis Awards, IC Design Contests, and Chip Awards (some samples are listed below):
  • Ph.D. Thesis Award, by Taiwan IC Design Society (TICD). Supervised student: Chih-Hsiu Lin, “High-performance Decision Feedback Equalizer Algorithms and Architectures,” 2005
  • Prof. Shen’s Thesis Award, by Taiwan IC Design Society (TICD). Supervised student: Cheng-Shing Wu, “Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Architecture,” 2002
  • Master Thesis Award, from the Chinese Institute of Electrical Engineering (CIEE). Supervised student: Jye-Jong Leu, “Design Methodology for Booth-encoded Montgomery Module Design for RSA Cryptosystem,” 2000
  • 2006, 2007: Best Master Thesis Award from Graduate Institute of Electronics Engineering, Supervised students: Xin-Yu Shi and Tzu-Hao Yu
  • 2004, 2007, 2009: 3 times Best Advisor Award, Golden Silicon IC Design Contest (the largest IC design contest in Taiwan), Macronix International Corporation (MXIC) Education Foundation, Taiwan
  • 2004, 2005, 2007~2010: Advisor of 8 times “Annual Chip Design Award” by National Chip Implementation Center (CIC), National Applied Research Labs (NARL), for innovative chip designs in Noise-tolerant circuits and DSP engines for communication systems

Experience

  • Director (Chairman), Graduate Institute of Electronics Engineering (GIEE), National Taiwan University (NTU), Taipei, TAIWAN, Aug. 2016 – Now
  • IEEE Fellow, 2015, For contributions to DSP algorithms and VLSI designs for communication IC/So
  • Distinguished Professor, Graduate Institute of Electronics Engineering, and Electrical Engineering Department, National Taiwan University (NTU), Taipei, TAIWAN, Aug. 2015 - Now
  • Deputy Director, Graduate Institute of Electronics Engineering (GIEE) of National Taiwan University, Aug. 2012- Jul. 2013
  • Deputy General Director of SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, TAIWAN, Aug. 2007- Dec. 2009
  • Member of Technical Staff (MTS) at AT&T Bell Laboratories, Murray Hill, NJ, Aug. 1995- July. 1996

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Publications

Journal Papers
2016
Yu-Min Lin, Yi Chen, Nai-Shan Huang, and An-Yeu (Andy) Wu, “Low-Complexity Stochastic Gradient Pursuit (SGP) Algorithm and Architecture for Robust Compressive Sensing Reconstruction,” in IEEE Trans. Signal Processing, issue 99, pp. 638-650, Feb. 2017. (pdf)
Yu-Min Lin, Jie-Fang Zhang, Jing Geng, and An-Yeu (Andy) Wu, “Structural Scrambling of Circulant Matrices for Cost-effective Compressive Sensing,” in Journal of Signal Processing Systems, October. 2016. (pdf)
Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu and An-Yeu (Andy) Wu, “Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing,” accepted for publication in IEEE Trans. Circuits and Systems-I: Regular Papers (TCAS-I), July 2016 (pdf)
Hung-Yi Cheng, and An-Yeu (Andy) Wu, "Unified Low-complexity Decision Feedback Equalizer with Adjustable Double Radius Constraint," in Digital Signal Processing(DSP), vol.51, pp. 82-91, April. 2016. (pdf)
2015
Sung-Chun Tang, Hsiao-I Jen, Yen-Hung Lin, Chi-Sheng Hung, Wei-Jung Jou, Pei-Wen Huang, Jiann-Shing Shieh, i-Lwun Ho, Dar-Ming Lai, An-Yeu Wu, Jiann-Shing Jeng, Ming-Fong Chen, "Complexity of heart rate variability predicts outcome in intensive care unit admitted patients with acute stroke," in Journal of Neurology, Neurosurgery and Psychiatry (JNNP), vol. 86, issue 1, pp.95-100, Jan. 2015. (pdf)
Kun-Chih Chen, En-Jui Chang, Huai-Ting Li, and An-Yeu (Andy) Wu, “RC-based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-based 3D NoCs,” in IEEE Trans. Parallel and Distributed Systems, vol. 26, issue 1, pp. 206-218, Jan. 2015. (pdf)
En-Jui Chang, Hsien-Kai Hsin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Regional ACO-Based Cascaded Adaptive Routing for Load Balancing in Mesh-Based Network-on-Chip Systems,” in IEEE Trans. Computers(TC), vol. 64, issue 3, pp. 868-875, March 2015. (pdf)
Yu-Min Lin, Huai-Ting Li, Ming-Han Chung, and An-Yeu (Andy) Wu, “Byte-Reconfigurable LDPC Codec Design with Application to High-Performance ECC of NAND Flash Memory Systems,” in IEEE Trans. Circuits and Systems-I: Regular Papers (TCAS-I), vol. 62, No. 7, pp. 1794-1804, July 2015 (full paper, SCI, EI) (pdf)
Hsien-Kai Hsin, En-Jui Chang, Kuan-Yu Su, and An-Yeu (Andy) Wu, “Ant Colony Optimization-based Adaptive Network-on-Chip Routing Framework Using Network Information Region,” in IEEE Trans. Computers(TC), vol. 64, issue. 8, pp. 2119-2131, Aug. 2015. (pdf)
Kun-Chih (Jimmy) Chen, Chih-Hao Chao, An-Yeu (Andy) Wu, "Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managementse," in IEEE Circuits and Systems Magazine, vol. 15, issue 4, pp.45-69, Nov. 2015. (pdf)
2014
Wen-Chung Shen, Yu-Hao Chen, and An-Yeu (Andy) Wu, “Low-Complexity Sinusoidal-Assisted EMD (SAEMD) Algorithms for Solving Mode-Mixing Problems in HHT,” in Digital Signal Processing(DSP), vol.24, pp. 170-186, Jan. 2014. (pdf)
En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, issue 1, pp. 113-126, Jan. 2014. (pdf)
Yu-Hao Chen, Yu-Min Lin, Kuan-Yu Ho, An-Yeu Wu, and Pai-Chi Li, “Low-Complexity Motion-Compensated Beamforming Algorithm and Architecture for Synthetic Transmit Aperture in Ultrasound Imaging,” in IEEE Trans. Signal Processing (TSP), vol. 62, no.4, pp. 840-851, Feb. 2014 (Full paper, SCI, EI). (pdf) (fix)
Hsien-Kai Hsin, En-Jui Chang, and An-Yeu (Andy) Wu, “Spatial-Temporal Enhancement of ACO-based Selection Schemes for Adaptive Routing in Network-on-Chip Systems,” in IEEE Trans. Parallel and Distributed Systems (TPDS), vol. 25, issue 6, pp. 1626-1367, June 2014. (pdf)
Hsien-Kai Hsin, En-Jui Chang, Chia-An Lin, and An-Yeu (Andy) Wu, “Ant Colony Optimization-Based Fault-Aware Routing in Mesh-based Network-on-Chip Systems,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, issue 11, pp. 1693-1705, Nov. 2014. (pdf)
Sung-Chun Tang, Hsiao-I Jen, Yen-Hung Lin, Chi-Sheng Hung, Wei-Jung Jou, Pei-Wen Huang, Jiann-Shing Shieh, Yi-Lwun Ho, Dar-Ming Lai, An-Yeu Wu, Jiann-Shing Jeng, Ming-Fong Chen, “Complexity of Heart Rate Variability Predicts Outcome in Intensive Care Unit Admitted Acute Stroke Patients,” in Journal of Neurology, Neurosurgery and Psychiatry (JNNP), Online available. (pdf)
2013
Jie-Ren Shih, Yongbo Hu, Ming-Chun Hsiao, Ming-Shing Chen, Wen-Chung Shen, Bo-Yin Yang, An-Yeu Wu, and Chen-Mou Cheng, “Securing M2M with Post-Quantum Public-Key Cryptography,” in IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 3, no. 1, pp. 106-116, March 2013. (pdf)
Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, and An-Yeu Wu, “Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems,” in IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol.21, no.4, pp.747-760, April 2013. (pdf)
Yi-Hsuan Lin, Yu-Hao Chen, Chun-Yuan Chu, Cheng-Zhou Zhan and An-Yeu Wu, “Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems,” in IEEE Trans. Signal Processing, vol. 61, no.14, pp. 3545-3562, July 2013. (pdf)
Wen-Chung Shen, Hsiao-I Jen, and An-Yeu (Andy) Wu, “New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform,” in IEEE Trans. Circuits and Systems, Part-II: Express Briefs (TCAS-II), vol. 60, no. 8, pp. 532-536, Aug. 2013 (SCI, EI). (pdf)
Chih-Hao Chao, Kun-Chih Chen, Tsu-Chu Yin, Shu-Yen Lin and An-Yeu (Andy) Wu, “Transport Layer Assisted Routing for Run-Time Thermal Management of 3D NoC Systems,” in ACM Trans. Embedded Computing Systems, vol.13, no.1, article 11, Aug. 2013. (pdf)
Hsien-Kai Hsin, En-Jui Chang and An-Yeu Wu. "Implementation of ACO-based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems," in IEEE Embedded Systems Letters, vol. 5, No. 3, pp.46-49, Sept. 2013. -(pdf)
Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, and An-Yeu (Andy) Wu, “Topology-Aware Adaptive Routing for Non-Stationary Irregular Mesh in Throttled 3D NoC Systems,” in IEEE Trans. Parallel and Distributed Systems, vol.24, no.10, pp. 2109-2120, Oct. 2013. (Full paper, SCI, EI). (pdf)
Cheng-Hung Lin, Chun-Yu Chen, En-Jui Chang, and An-Yeu (Andy) Wu, “Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems,” in Journal of Signal Processing Systems (JSPS), vol. 73, no. 2, pp. 109-122, Nov. 2013. (pdf)
Chih-Hao Chao, Kun-Chih Chen, and An-Yeu (Andy) Wu, “Routing-Based Traffic Migration and Buffer Allocation Schemes for Three-Dimensional Network-on-Chip Systems with Thermal Limit,” in IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol.21, no.11, pp. 2118-2131, Nov. 2013. (pdf)
2012
Cheng-Zhou Zhan, Yen-Liang Chen and An-Yeu Wu, "Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems," in IEEE Trans. Signal Processing(TSP), vol. 60, pp. 3264-3277, June 2012. (Full paper, SCI, EI). (pdf)
Min-An Chao, Xin-Yu Shih and An-Yeu Wu, "Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders," in Journal of Signal Processing Systems (JSPS), vol. 68, No. 2, pp. 183-202, Aug. 2012. (Full paper, SCI, EI). (pdf)
Chun-Yuan Chu and An-Yeu Wu, "Power-Efficient State Exchange Scheme for Low Latency SMU Design of Viterbi Decoder," in Journal of Signal Processing Systems (JSPS), vol. 68, No. 2, pp. 233-245, Aug. 2012 (Full paper, SCI, EI). (pdf)
Yu-Hao Chen, Zih-Ling Liu, I-Hsuan Lee, and An-Yeu (Andy) Wu, “Motion Artifact Elimination Algorithm and Architecture for Eigen-based Clutter Filter in Color Doppler Processing,” in International Journal of Electrical Engineering(IJEE), vol. 19, no. 6, pp. 245-254, Dec. 2012. (pdf)
2011
Cheng-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, "Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding," in IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 2, pp. 305-318, Feb 2011. (Full paper, SCI, EI). (pdf)
Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, and An-Yeu Wu, "Parallel Architecture Core (PAC) - the First Multi-core Application Processor SoC in Taiwan Part I: Hardware architecture & Software Development Tools," in Journal of Signal Processing Systems (JSPS), vol. 62, No. 3, pp. 373-382, Mar. 2011 (Full paper, SCI, EI). (pdf)
Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, An-Yeu Wu, "Parallel Architecture Core (PAC) - the First Multi-core Application Processor SoC in Taiwan Part II: Application Programming," in Journal of Signal Processing Systems (JSPS), vol. 62, No. 3, pp. 383-402, Mar. 2011 (Full paper, SCI, EI). (pdf)
Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, and An-Yeu Wu, “A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks, ” in Design Automation for Embedded Systems, vol.15, no.2, pp. 111-132, April 2011. (Full paper, SCI, EI). (pdf)
Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, and An-Yeu Wu, "Multi-prediction particle filter for efficient parallelized implementation," on-line publication in EURASIP Journal on Advances in Signal Processing, Vol. 2011, Number 1/53, Sept 2011 (Full paper, SCI, EI). (pdf)
2010
Yen-Liang Chen and An-Yeu Wu, “Generalized Pipelined Tomlinson–Harashima Precoder Design Methodology With Build-In Arbitrary Speed-Up Factors,” IEEE Trans. Signal Processing, vol. 58, no.4, pp. 2375-2382, April 2010. (Full paper, SCI, EI) (pdf)
Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm,” in IEEE Trans. Circuits and Systems, Part-II: Express Briefs, vol. 57, no. 6, pp. 430-434, June 2010. (SCI, EI) (pdf)
2009
Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu, and Tsung-Han Tsai, "Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder," in IEEE Trans. Circuits and Systems Part I: Regular Paper, vol. 56, no. 5, pp. 1005-1016, May 2009 (Full paper, SCI, EI). (pdf)
Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu Wu, "Multilevel LINC system designs for power efficiency enhancement of transmitters," IEEE Journal of Selected Topics in Signal Processing. (JSTSP), vol.3, no. 3, pp. 523-532, June 2009 (Full paper, SCI, EI). (pdf)
Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, and An-Yeu Wu, "Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System," International Journal of Electrical Engineering (IJEE), vol. 16, no. 3, pp. 203-212, June 2009 (Full paper, SCI, EI). (pdf)
Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, and An-Yeu Wu, "Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor," International Journal of Electrical Engineering (IJEE), vol. 16, no. 3, pp. 213-222, June 2009 (Full paper). (pdf)
I-Chyn Wey, You-Gang Chen, Chang-Hong Yu, An-Yeu Wu, and Jie Chen, "Design and Implementation of Cost-Efficient Probabilistic-Based Noise-Tolerant VLSI Circuits," IEEE Trans. Circuits and Systems Part-I: Regular Papers, vol. 56, no. 11, pp. 2411 - 2424, Nov. 2009 (Full paper, SCI, EI). (pdf)
Before 2008

Index

Conference Papers

2016
Shih-Ming Shan, Sung-Chun Tang, Pei-Wen Huang, Yu-Min Lin,Wei-Han Huang, Dar-Ming Lai, An-Yeu Wu, "Reliable PPG-based Algorithm in Atrial Fibrillation Detection," in Proc. IEEE BioMedical Circuits and Systems Conference, pp. 340-343, Shanghai, China, Oct. 2016. (pdf)
Yu-Hsin Liu, Chiang-Hen Chen, Cheng-Rung Tsai, and An-Yeu (Andy) Wu, “Multilevel-DFT based Low-Complexity Hybrid Precoding for Millimeter Wave MIMO Systems ,” in Proc. IEEE Conference on Signal Processing, Communications and Computing (ICSPCC-2016), pp. 588-592, Hong Kong, China, Aug. 2016. (pdf)
Yu-Min Lin, Hung-Chi Kuo, and An-Yeu (Andy) Wu, “Robust LMS-based Compressive Sensing Reconstruction Algorithm for Noisy Wireless Sensor Networks,” in Proc. IEEE Int. Conf. Intelligent Green Building and Smart Grid (IGBSG-2016), pp. 1-5, Prague, Czech Republic, June. 2016. (pdf)
Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu (Andy) Wu, “Filter-Based Dual-Voltage Architecture for Low-Power Long-Word TCAM Design,” in Proc. IEEE Int. Conf. Intelligent Green Building and Smart Grid (IGBSG-2016), pp. 165-169, Prague, Czech Republic, June. 2016. (pdf)
Ching-Yao Chou, Yi-Chieh Ho, Huai-Ting Li, and An-Yeu (Andy) Wu, "Sniper-TEVR: Core-Variation Simulation Platform with Register-Level Fault Injection for Robust Computing in CMP System," in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’16), pp. 1-4, Hsinchu, Taiwan, April 2016. (pdf)
2015
(Student Travel Grant) Yu-Min Lin, Yi Chen, Hung-Chi Kuo, and An-Yeu Wu, “Compressive sensing based ECG telemonitoring with personalized dictionary basis,” in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS-2015), pp. 1-4, Atlanta, USA, Oct. 2015. (pdf)
Cheng-Rung Tsai, Ming-Chun Hsiao, Wen-Chung Shen, An-Yeu (Andy) Wu, and Chen-Mou Cheng, “A 1.96mm2 Low-Latency Multi-Mode Crypto-Coprocessor for PKC-based IoT Security Protocols,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2015), pp. 834-837, Lisbon, Portugal, May 2015. (pdf)
Pei-Wen Huang, Sung-Chun Tang, Yu-Min Lin, You-Cheng Liu, Wei-Jung Jou, Hsiao-I Jen, Dar-Ming Lai, An-Yeu Wu, “Predicting Stroke Outcomes based on Multi-modal Analysis of Physiological Signals,” in IEEE International Conference on Digital Signal Processing (DSP 2015), pp. 454-457, Singapore, July. 2015. (pdf)
Jie-Fang Zhang, Jing Geng, Yu-Min Lin, and An-Yeu (Andy) Wu, "Low Memory-Cost Scramble Methods for Constructing Deterministic CS Matrix," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2015),pp. 1-6, Hangzhou, China, Oct. 2015. (pdf)
Yi-Mu Tu, Michael C. Chang, Yu-Min Lin, and An-Yeu (Andy) Wu, "Dynamic Group Allocation Reconstruction for Group Sparse Signals," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2015),pp. 1-5, Hangzhou, China, Oct. 2015. (pdf)
(SiPS Best Student Paper Award) Jiachen Liu, Hung-Yi Cheng, Ching-Chun Liao, An-Yeu (Andy) Wu, "Scalable Compressive Sensing-Based Multi-User Detection Scheme for Internet-of-Things Applications," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2015),pp. 1-6, Hangzhou, China, Oct. 2015. (pdf)
Wei-Ching Chu, Huai-Ting Li, Ching-Yao Chou, An-Yeu (Andy) Wu, "Variation-Aware Core-Level Redundancy Scheme for Reliable DSP Computation in Multi-Core Systems," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2015),pp. 1-5, Hangzhou, China, Oct. 2015. (pdf)
Wei-Lun Hung, Chiang-Hen Chen, Ching-Chun Liao, Cheng-Rung Tsai, An-Yeu (Andy) Wu, "Low-Complexity Hybrid Precoding Algorithm based on Orthogonal Beamforming Codebook," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2015),pp. 1-5, Hangzhou, China, Oct. 2015. (pdf)
Huai-Ting Li, Ding-Yuan, Lee, Kun-Chih Chen, and An-Yeu (Andy) Wu, "An Algorithmic Error-Resilient Scheme for Robust LDPC Decoding," in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’15),pp. 1-4, Hsinchu, Taiwan, April 2015. (pdf)
2014
Kun-Chih Chen, Huai-Ting Li, and An-Yeu (Andy) Wu, “LMS-based Adaptive Temperature Prediction Scheme for Proactive Thermal-aware Three-Dimensional Network-on-Chip Systems,” in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’14), pp. 199-202, Hsinchu, Taiwan, April 2014. -(pdf)
(Best Paper Award) Yuan-Sheng Lee, Hsien-Kai Hsin, Kun-Chih Chen, En-Jui Chang, and An-Yeu (Andy) Wu, “Thermal-aware Dynamic Buffer Allocation for Proactive Routing Algorithm on 3D Network-on-Chip Systems,” in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’14), pp. 191-194, Hsinchu, Taiwan, April 2014. -(pdf)
Hung-Yi Cheng, Chun-Yuan Chu, Yen-Liang Chen, and An-Yeu (Andy) Wu, “Robust Decision Feedback Equalizer Scheme by Using Sphere-Decoding,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2014), pp. 5074-5077, Florence, Italy, May 2014. -(pdf)
Yu-Min Lin, Yu-Hao Chen, Ming-Han Chung and An-Yeu (Andy) Wu, “High-Throughput QC-LDPC Decoder with Cost-Effective Early Termination Scheme for Non-Volatile Memory Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2014), pp. 2732-2735, Melbourne, June 2014. -(pdf)
Pei-Wen Huang, Wei-Jung Jou, Yu-Min Lin, Hsiao-I Jen, Sung-Chun Tang, Dar-Ming Lai, and An-Yeu (Andy) Wu, “Trend-extracted MSE Based on Adaptive Aligned EEMD with Early Termination Scheme,”in Proc. IEEE Workshop on Signal Processing Systems (SiPS - 2014), pp.162-167, Belfast, UK, Oct. 2014. -(pdf)
Wei-Jung Jou, Pei-Wen Huang, Yu-Min Lin, Sung-Chun Tang, Dar-Ming Lai, An-Yeu Wu, “A Stroke Severity Monitoring System Based on Quantitative Modified Multiscale Entropy,” in IEEE Biomedical Circuits and Systems Conference (BioCAS-2014), pp.41-44, Lausanne, Switzerland, Oct. 2014. -(pdf)
Shih-Chieh Lin, En-Jui Chang, Yu-Yin Chen, Hsien-Kai Hsin, and An-Yeu (Andy) Wu, “High Performance Adaptive Routing for Network-on-Chip Systems with Express Highway Mechanism,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2014), pp.1-4, Okinawa, Japan, Nov. 2014. (pdf)
Nai-Shan Huang, Yu-Min Lin, Yi Chen, and An-Yeu (Andy) Wu, “Adaptive Filter-based Reconstruction Engine Design for Compressive Sensing,” in Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2014), pp.499-502, Okinawa, Japan, Nov. 2014. (pdf)
2013
Kun-Chih Chen, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Thermal Management Unit with Vertical Throttling Scheme for Proactive Thermal-aware 3D NoC Systems,” in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2013), pp.118-121, Hsinchu, Taiwan, April 2013. -(pdf)
Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu Wu, "Hybrid Path-Diversity-Aware Adaptive Routing with Latency Prediction Model in Network-on-Chip Systems," in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2013), pp.348-351, Hsinchu, Taiwan, April 2013. -(pdf)
Kun-Chih Chen, Che-Chuan Kuo, Hui-Shun Hung, and An-Yeu (Andy) Wu, “Traffic- and Thermal-aware Adaptive Beltway Routing for Three Dimensional Network-on-Chip Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2013), pp.1660-1663, Beijing, May 2013. -(pdf)
Yu-Hao Chen, Kuan-Yu Ho, and An-Yeu (Andy) Wu, “VLSI Implementation of Real-Time Motion Compensated Beamforming in Synthetic Transmit Aperture Imaging,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2013), pp.1893-1896, Beijing, May 2013. -(pdf)
Ming-Han Chung, Yu-Min Lin, Cheng-Zhou Zhan, An-Yeu(Andy) Wu, “Cost-Effective Scalable QC-LDPC Decoder Designs for Non-Volatile Memory Systems,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2013), pp. 2625-2628, Vancouver, Canada, May 2013. -(pdf)
Zih-Ling Liu, Yu-Hao Chen, Cheng-Zhou Zhan, An-Yeu (Andy) Wu, “Motion Artifact Elimination Algorithm with Eigen-based Clutter Filter for Color Doppler Processing,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2013), pp. 1066-1069, Vancouver, Canada, May 2013. -(pdf)
Chia-An Lin, Hsien-Kai Hsin, En-Jui Chang, and An-Yeu (Andy) Wu, “ACO-Based Fault-Aware Routing Algorithm for Network-on-Chip Systems,” in IEEE Workshop on Signal Processing Systems, pp.342-347, Taipei, Oct. 2013. -(pdf)
I-Hsuan Lee, Yu-Hao Chen, Nai-Shan Huang, and An-Yeu (Andy) Wu, “Accelerating Motion-Compensated Adaptive Color Doppler Engine on CUDA-Based GPU Platform,” in IEEE Workshop on Signal Processing Systems, pp.225-230, Taipei, Oct. 2013. -(pdf)
Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, and An-Yeu (Andy) Wu, “Proactive Thermal-Budget-Based Beltway Routing Algorithm for Thermal-Aware 3D NoC Systems,” Int’l Symp. System-on-Chip, pp. 1-4, Tampere, Oct. 2013. -(pdf)
2012
Kun-Chih Chen, Chi-Hao Chao, Shu-Yen Lin, Hui-Shung Hung, and An-Yeu (Andy) Wu, “Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems,” IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2012), pp. 23-25, April 2012. (pdf)
Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu (Andy) Wu, “Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems” in Proc. IEEE 6th Int. Symp. Embedded Multicore SoCs (MCSoC-2012), pp.175-182, Fukushima, Japan, Sept. 2012. -(pdf)
Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung and An-Yeu Wu, “Traffic-Balanced Topology-Aware Multiple Routing Adjustment For Throttled 3D NoC Systems ,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 120-124, Oct. 2012. -(pdf)
Yi-Hsuan Lin, Cheng-Zhou Zhan, Chun-Yuan Chu and An-Yeu Wu, “A Low-Complexity Grouping FFT-Based Codebook Searching Algorithm In LTE System ,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 161-166, Oct. 2012. -(pdf)
Kuan-Yu Su, Hsien-Kai Hsin, En-Jui Chang and An-Yeu Wu, “ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 209-214, Oct. 2012. -(pdf)
Yu-Hao Chen, Kuan-Yu Ho, Cheng-Zhou Zhan and An-Yeu Wu, “Coherent Image Herding of Inhomogeneous Motion Compensation for Synthetic Transmit Aperture in Ultrasound Image,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 254-257, Oct. 2012. -(pdf)
2011
Shu-Yen Lin, Tzu-Chu Yin, Hao-Yu Wang and An-Yeu Wu, "Traffic-and Thermal-Aware Routing for Throttled Three-Dimensional Network-on-Chip Systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2011), pp. 320-323 ,April 2011. - (pdf)
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu , "Multi-Pheromone ACO-based Routing in Network-on-Chip System Inspired by Economic Phenomenon ,” in 24th IEEE International SOC Conference (SOCC-2011), pp. 273-277, Sep. 2011. - (pdf)
Chih-Hao Chao, Tzu-Chu Yin, Shu-Yen Lin, An-Yeu Wu "Transport Layer Assisted Routing for Non-Stationary Irregular Mesh of Thermal-Aware 3D Network-on-Chip Systems ,” in 24th IEEE International SOC Conference (SOCC-2011), pp. 284-289, Sep. 2011.- (pdf)
Cheng-Zhou Zhan, Zih-Ling Liu, and An-Yeu Wu, “Adaptive Thresholding Incorporating Temporal And Spatial Information With Eigen-Based Clutter Filter For Color Doppler Processing In Ultrasonic Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2011), pp. 361-366, Oct. 2011. (pdf)
Tzu-Chu Yin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Transport Layer Assisted Routing for Thermal-Aware 3D Network-on-Chip,” in Asia Pacific Signal and Information Processing Association (APSIPA), Oct. ,2011 (pdf)
C.-H. Lin, E.-J. Chang, C.-Y. Chen, and A.-Y. Wu, “A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards,” in Proc. IEEE Int. Symp. Integrated Circuits (ISIC), pp. 178-181, Dec., 2011(pdf)
2010
(Best Paper Award) Kai-Yuan Jheng, Chih-Hao Chao, Hao-Yu Wang, and An-Yeu Wu, "Traffic-thermal mutual-coupling co-simulation platform for three-dimensional Network-on-Chip," in Proc. int. Sym. VLSI Design Automation and Test (VLSI-DAT), pp.135-138, April 2010. - (pdf)
Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, and An-Yeu Wu, "Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems," in Proc. ACM/IEEE int. Sym. Networks-on-Chip (NOCS), pp.223-230, May 2010. - (pdf)
En-Jui Chang, Chih-Hao Chao, Kai-Yuan Jheng, Hsien-Kai Hsin and An-Yeu Wu, “ACO-based Cascaded Adaptive Routing for Traffic Balancing in NoC Systems,” in IEEE International conference on Green Circuit and Systems, pp.317-322, June 2010.- (pdf)
Yen-Liang Chen, Ting-Jyun Jheng, Cheng-Zhou Zhan, and An-Yeu Wu, “A 2.17 mm2 125mW Reconfigurable SVD Chip for IEEE 802.11n System,” in Proc. IEEE Conference on European Solid-State Circuits (ESSCIRC-2010), pp. 534-537, Sept. 2010. - (pdf)
Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, and An-Yeu Wu, “Multi-Prediction Particle Filter for Efficient Memory Utilization,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 295-298, Oct. 2010. - (pdf)
Chih-Hao Chao, Chun-Yuan Chu, Min-An Chao, and An-Yeu Wu, “Cost-Effective Constrained Particle Filter For Indoor Location,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 290-294, Oct. 2010. - (pdf)
Min-An Chao, Chun-Yuan Chu, Chih-Hao Chao, and An-Yeu Wu, “Efficient Parallelized Particle Filter Design on CUDA,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 299-304, Oct. 2010. - (pdf)
Kai-Ting Chang, Cheng-Zhou Zhan, and An-Yeu Wu, “Joint-Decision Adaptive Clutter Filter and Motion-Tracking Adaptive Persistence for Color Doppler Processing in Ultrasonic Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 249-253, Oct. 2010. - (pdf)
Cheng-Zhou Zhan, Kai-Ting Chang, Yu-Hao Chen, Pai-Chi Li, and An-Yeu Wu, " Motion-Tracking Adaptive Persistence and Adaptive-Size Median Filter for Color Doppler Processing in Ultrasonic Systems on Multi-core Platform," in Proc. IEEE Conference on Biomedical Circuits and Systems (BioCAS-2010), Nov, 2010. - (pdf)
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Yeu Wu, "Regional ACO-based Routing for Load-Balancing in NoC Systems,” in IEEE Second World Congress on Nature and Biologically Inspired Computing (NaBIC-2010), pp. 377-383, Dec. 2010. - (pdf)
2009
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, "A 52-mW 8.29mm2 19-mode LDPC Decoder Chip for Mobile WiMAX Applications," in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC-2009), Yokohama, JAPAN, pp. 121-122, Jan. 2009.- (pdf)
Cheng-Zhou Zhan, Kai-Yuan Jheng, Yen-Lian Chen, Ting-Jhun Jheng, and An-Yeu Wu, "High-Convergence-Speed Low-Computation-Complexity SVD Algorithm for MIMO-OFDM Systems," in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2009), Hsinchu, Taiwan, pp. 195-198,April, 2009.- (pdf)
Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, Chih-Hao Chao, and An-Yeu Wu, "Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor Systems" in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2009), Hsinchu, Taiwan, pp. 72-75,April, 2009.- (pdf)
Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, and An-Yeu Wu, "A Triple-Mode LDPC Decoder Design for IEEE 802.11n System," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2445-2448, May, 2009.- (pdf)
Shu-Yen Lin, Chan-cheng Hsu, and An-Yeu Wu, "A Scalable Built-in Self-Test/Self-Diagnosis Architecture for 2D-mesh Based Chip Multiprocessor Systems," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2009), Taipei, Taiwan, pp. 2317-2320, May, 2009. - (pdf)
Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, and An-Yeu Wu, “A Channel-Adaptive Early Termination strategy for LDPC decoders ” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2009), Tampere, Finland, pp. 226-231, Oct. 2009. (pdf)
I-Yao Chuang, Chi-Wen Chang, Tso-Yi Fan, Jen-Chieh Yeh, Kung-Ming Ji, Jui-Liang Ma, An-Yeu (Andy) Wu, and Shih-Yin Lin, "PAC Duo SoC performance analysis with ESL design methodology," in IEEE 8th International Conference, Changsha, Hunan, pp. 399-402, Oct. 2009. -(pdf)
(Highlighted Paper) Xin-Yu Shih, Cheng-Zhou Zhan, and An-Yeu Wu, "A Real-Time Programmable LDPC Decoder Chip for Arbitrary QC-LDPC Parity Check Matrices," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2009), Taipei, TAIWAN, pp. 369-372, Nov. 2009. - (pdf)
Before 2008

Index

   
Chapters in Books
1. K. J. R. Liu and An-Yeu Wu, “Algorithms and Architectures for Split Recursive Least Squares,” in VLSI Signal Processing VII (J. Rabaey, P.M. Chau, and J. Eldon, eds.), pp.460-469, IEEE Press, 1994.
2. An-Yeu Wu, K. J. R. Liu, Z. Zhang, K. Nakajima, S.-C. Liu, and A. Raghupathy, “Algorithm-Based Low-Power Digital Signal Processing System Design: Methodology and Verification,” in VLSI Signal Processing VIII (T. Nishitani and K. K. Parhi, eds.), pp.277-286, IEEE Press, 1995.
3. K. J. R. Liu and An-Yeu Wu, “Chapter 18: Systolic RLS Adaptive Filtering,” in Digital Signal Processing for Multimedia Systems, Part II: Programmable and Custom Architectures and Algorithms (K. K. Parhi and T. Nishitani, eds.), pp. 487-518, Marcel Dekker, Inc. (New York), 1999. 
4. Shu-Yen Lin, An-Yeu Wu, “Chapter 4: Routing Algorithms for Irregular Mesh-based Network-on-Chip,” in Multi-core Embedded System (Georgios Kornaros eds.), pp. 111-154, CRC Press, April 2010. 
5. Kun-Chih Chen, Chi-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Chapter 12: Thermal- and Traffic-Aware Routing for 3D NoC Systems,” in Routing Algorithms in Networks-on-Chip (M. Palesi and M. Daneshtalab eds.), Springer, to appear in Nov. 2013. 
   
Patents(USA)
1. USA Patent, No. 6,157,938, “Fast Fourier Transform Device with Parallel Lattice Architecture,” by An-Yeu Wu, Tsun-Shan Chan, and Bor-Min Wang, Granted on 2000/12/5.
2. USA Patent, No. 6,697,424, “Fast Convergent Pipelined Adaptive Decision Feedback Equalizer Using Post-cursor Processing Filter,” by Meng-Da Yang, and An-Yeu Wu, Granted on 2004/2/24. .
3. USA Patent, No. 6,985,919, “Time-recursive Lattice Structure for IFFT in DMT Application,” by Chi-Li Yu and An-Yeu Wu, Granted on 2006/1/10. 
4. USA Patent, No. 7,047,269, “CORDIC Method and Architecture Applied in Vector Rotation,” by Cheng-Shing Wu, Chia-Ho Pan, and An-Yeu Wu, Granted on 2006/5/16. 
5. USA Patent, No. 7,054,896, “Method for Implementing a Multiplier-less FIR Filter,” by I-Hsien Lee, Cheng-Shing Wu, and An-Yeu Wu, Granted on 2006/5/30.
6. USA Patent, No. 7,200,221, “Methods and systems for providing multi-path echo cancellation,” by Cheng-Shing Wu and An-Yeu Wu, Granted on 2007/4/3.
7. USA Patent, No. 7,317,755, “Predicted parallel branch slicer and slicing method thereof,” by Meng-Da Yang, An-Yeu Wu, and Murphy Chen, Granted on 2008/1/8. 
8. USA Patent, No. 7,483,482, “Soft-threshold-based multi-layer decision feedback equalizer and decision method,” by An-Yeu Wu and Chih Hsiu Lin, Granted on 2009/1/27. 
9. USA Patent, No. 7,545,871, “Discrete multi-tone System having DHT-based frequency-domain equalizer,” by Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang, and An-Yeu Wu, Granted on 2009/6/9.
10. USA Patent, No. 7,602,844, “On-line step-size calculation using signal power estimation and tone grouping of the frequency-domain equalizer for DMT-based transceiver,” by Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang, and An-Yeu Wu, Granted on 2009/10/13.
11. USA Patent, No. 7,724,839, “Multilevel LINC Transmitter,” by Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao, and Posen Tseng, Granted on 2010/5/25. 
12. USA Patent, No. 7,826,553, “Multilevel LINC Transmitter,” by Yuan-Jyue Chen, Kai-Yuan Jheng, and An-Yeu Wu, Granted on 2010/11/02. 
13. USA Patent, No. 8,230,311, “Method and apparatus for Turbo code decoding,” by Cheng-Hung Lun and An-Yu Wu, Granted on 2012/7/24.
14. USA Patent, No. 8,275,060, “Codebook searching apparatus and thereof,” by Yen-Liang Chen, Cheng-Ming Chen, Pang-An Ting, and An-Yu Wu, Granted on 2012/9/25.
15. USA Patent, No. 8,296,622, “Programmable LDPC code decoder and decoding method thereof ,” by Xin Yu Shih and An Yeu Wu, Granted on 2012/10/23. 
16. USA Patent, No. 8,321,488, “Singular value decomposing method and related singular value decomposing device,” by Cheng-Zhou Zhan, Yen-Liang Chen, Ting-Jhun Jheng and An-Yeu Wu, Granted on 2012/11/27.  
Patents(Taiwan and Other Countries)
1. ROC (Taiwan) Patent, No. 127231, “Fast Fourier Transform Device with Parallel Lattice Architecture (具有平行架構之快速傅利葉轉換裝置),” by An-Yeu Wu, Tsun-Shan Chan and Bor-Ming Wang, Granted on 2001/1/11.
2. ROC (Taiwan) Patent, No. 522657, “A PGZ algorithm based Mutimode Reed-Solomon decoder method (基於PGZ 演算法的多模式李得-所羅門解碼器及其方法),” by Huai-Yi Hsu, Sheng-Feng Wang, An-Yeu Wu and Ho-Wen Chen, Granted on 2003/3/1.
3. ROC (Taiwan) Patent, No. 583579, “CORDIC Algorithms and Architectures for Vector Rotational Applications (應用在向量旋轉器之座標旋轉數位計算器運算方法及架構),” by Cheng-Shing Wu, Chia-Ho Pan, and An-Yeu Wu, Granted on 2004/4/11. 
4. Korean Patent, No. 428611, “Mixed-time-frequency Domain Equalizer for Digital Subscriber Loop (用於同步數位系統等化混合時域及頻域之方法),” by Chih-Chi Wang, An-Yeu Wu, and Bor-Min Wang, Granted on 2004/4/16.  
5. ROC (Taiwan) Patent, No. I220603, “Multi-Path Echo Cancellation Method and System (提供多路徑回聲消除之方法與系統),” by Cheng-Shing Wu, and An-Yeu Wu, Granted on 2004/8/21.
6. ROC (Taiwan) Patent, No. I237789, “Predicted Parallel Branch Slicer and Corresponding Method (預測並行分支量階器與量階方法),” by Meng-Da Yang, An-Yeu Wu, and Murphy Chen, Granted on 2005/8/11.
7. ROC (Taiwan) Patent, No. I258085, “Soft-threshold-based multi-layer decision feedback equalizer and decision method (多層軟性決策回饋等化器及決策方法),” by Chih-hsiu Lin and An-Yeu Wu, Granted on 2006/07/11.
8. ROC (Taiwan) Patent, No. I325256, “Discrete Multi-Tone System Having DHT-Based Frequency-Domain Equalizer (使用離散式哈特利轉換頻域等化器的離散多重音調通信系統),” by Muh-Tian Shiue, Chorng-Kuang Wang, Chih-Feng Wu and An-Yeu Wu, Granted on 2010/05/21.
9. ROC (Taiwan) Patent, No. I339972, “Multilevel LINC Transmitter (多級具有非線性組件之線性發射器),” by Yuan-Jyue Chen, Kai-Yuan Jheng and An-Yeu Wu, Granted on 2011/04/01. 
10. ROC (Taiwan) Patent, No. I339956, “Method and Apparatus for Convolutional Turbo Decoding (渦輪解碼器以及解碼方法),” by Cheng-Hung Lin and and An-Yeu Wu, Granted on 2011/04/01.  
11. ROC (Taiwan) Patent, No. I349445, “Multilevel LINC Transmitter (以非線性元件達成線性放大的多階傳輸器),” by Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao and Posen Tseng, Granted on 2011/09/21.
12. ROC (Taiwan) Patent, No. I377802, “Codebook Searching Apparatus and Method Thereof (編碼簿搜尋裝置及其方法),” by Cheng-Ming Chen, Yen-Liang Chen, Pang-An Ting and An-Yu Wu, Granted on 2012/11/21.
13. ROC (Taiwan) Patent, No. I380598, “Programmable LDPC Code Decoder and Decoding Method Thereof (可程式化的低密度奇偶校驗編碼之解碼裝置及其解碼方法),” by Xin-Yu Shih and An-Yeu Wu, Granted on 2012/12/21.
14. ROC (Taiwan) Patent, No. I393394, “Singular Value Decomposition Method and Device (奇異值分解方法及裝置),” by Cheng-Zhou Zhan, Yen-Liang Chen, Ting-Jhun Jheng and An-Yeu Wu, Granted on 2013/04/11. 
Technology Transfer

Technology

Authorizing Unit

Authorized Unit

Period of Contract

NSC Project ID #

Signal Decomposition System with Low-latency Empirical Mode Decomposition and Method Thereof

臺灣大學

臺灣大學

2016/04/11

N/A

Thernal Period System And Method Thereof

臺灣大學

臺灣大學

2016/08/01

N/A

Data Compression Engine for LCD Driver IC

臺灣大學

矽創電子股份有限公司

2013/02/01

N/A

應用於儲存記憶體之LDPC編解碼器設計

臺灣大學

威鋒電子股份有限公司

2011/01/15

N/A

小尺寸液晶顯示器控制IC之無失真資料壓縮編解碼器設計

臺灣大學

矽創電子股份有限公司

2010/09/01

N/A

適用於用戶線路之低成本低功率頻域等化器技術之實現

國科會/臺灣大學

誠致科技

2004/05~2004/05

NSC 93-2622-E-002-011-CC3

適用於超寬頻帶系統(UWB)之里德所羅門(RS)編解碼處理器

國科會/臺灣大學

智原科技

2005/12~2005/12

NSC 90-2218-E-002-040

DHT-based FFT/IFFT處理器

國科會/臺灣大學

誠致科技

2004/06~2004/06

NSC 90-2218-E-002-037

用戶線路之頻域等化器技術設計與研究

國科會/臺灣大學

誠致科技

2003/05~2003/05

NSC 92-2622-E-002-012-CC

Index