Related Paper List

[1]  L. Benini and G. De Micheli, ˇ§Networks on chip: a new paradigm for systems on chip design,ˇ¨ Proc. IEEE DATE, Mar. 2002, pp. 418ˇV419.
[2]  A. W. Topol et al., ˇ§Three-dimensional integrated circuits,ˇ¨ IBM J. Research Development, pp. 491ˇV506, Jul. 2006.
[3]  I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini, ˇ§A low-overhead fault tolerance scheme for TSV-based 3D network on chip links,ˇ¨ Proc. IEEE/ACM ICCAD, Nov. 2008, pp. 598ˇV602.
[4]  K. Puttaswamy and G. H. Loh, ˇ§Thermal herding: microarchitecture techniques for controlling hotspots in high-performance 3D-integrated processors,ˇ¨ Proc. IEEE HPCA, Feb. 2007, pp. 193ˇV204.
[5]  L. Shang, L. Peh, A. Kumar, and N. K. Jha, ˇ§Thermal modeling, characterization and management of on-chip networks,ˇ¨ Proc. IEEE MICRO, Dec. 2004, pp. 67ˇV78.
[6]  CFD-RC [Online]. Available: http://www.cfdrc.com/
[7]  ANSYS [Online]. Available: http://www.ansys.com/
[8]  W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron, ˇ§An improved HotSpot block-based thermal model with granularity considerations,ˇ¨ Proc. WDDD in conjunction with ISCA, Jun. 2007.
[9]  C. Addo-Quaye, ˇ§Thermal-aware mapping and placement for 3-D NoC designs,ˇ¨ Proc. IEEE Int. SOC Conf., Sep. 2005, pp. 25ˇV28.
[10] Noxim: network-on-chip simulator [Online]. Available: http://sourceforge.net/projects/noxim/
[11] J. Kim et al., ˇ§A novel dimensionally-decomposed router for on-chip communication in 3D architectures,ˇ¨ Proc. ISCA, 2007, pp. 138ˇV149.
[12] FEMLAB [Online]. Available: http://www.comsol.com/
[13] Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, ˇ§A 5-GHz mesh interconnect for a teraflops processor,ˇ¨ IEEE Micro, Sep.ˇVOct. 2007, pp. 51ˇV61.