Research Topics
Research Summary

After entering the academic field, Professor An-Yeu (Andy) Wu has been taking VLSI signal processing as the main research topic of his lab, and the research results are mainly applied to broadband communication IC design. Latest notable achievements are summarized as follows:


  1.Algorithm-based Low-power Design:

This study was the main subject of Prof. Wuˇ¦s doctoral thesis. The research series was not only published as many IEEE full-length journals, but also invited to be organized as a 48-page journal paper and published as Special Issue on ˇ§Multimedia Signal Processingˇ¨ in Proceedings of IEEE in 1998.


  2. Unified Vector Rotational CORDIC Family using ˇ§Angle Quantizationˇ¨ Perspective:

In the series of studies, Prof. Wu first proposed the idea of ˇ§Angle Quantizationˇ¨, AQ. Like Signed Power-of-Two (SPT) method can reduce the hardware cost of digital filters, AQ achieves lower computational complexity by using only several shift-and-add operations to meet the target angle. He re-examined the rotation algorithm of CORDIC (Coordinate Rotational Digital Computer) by the concept of AQ, and then proposed a brand-new design framework that could handle all vector rotations. Prof. Wuˇ¦s team derived a number of new computing algorithms and rotating structures, and published many IEEE full-length journals. In addition, the study of new rotation algorithms also received accreditation praise, such as

-          Paper on MVR-CORDIC was awarded ˇ§Prof. Shen Wenren Memorial Paper Awardˇ¨ in 2002.

-          Paper on EEAS-CORDIC was awarded ˇ§The Best Paper Award Nominationˇ¨ of the 2nd IEEE Asia-Pacific Conference on ASICs (AP-ASIC) in 2000.

3.Reconfigurable Communication Silicon IP Designs:


Reconfigurable Design has become a new VLSI design, which combines the efficiency and low-power of ASIC and flexibility of general-purpose processors. In recent years, the research team has researched all kinds of Reconfigurable Communication Silicon Intellectual Property (SIP), including
• Reconfigurable / multi-mode Reed Solomon Codec
• Dual-mode Turbo / Viterbi decoder for 3GPP
• Variable-length FFT Processor for OFDM-based Communication Systems

Part of the design results have been published in journals and international conference papers. Besides, these designs receive excellent awards from ˇ§Silicon Intellectual Property Design Contest" and "National Chip Implementation Center Excellent Chip Design.ˇ¨


4. Novel Adaptive Equal Design for Communication / Storage Systems:


Equalizer is the core technology for communications and storage systems. We must to considerate the speed of computing (such as 8 ns data rate in Gigabit Ethernet) and the complexity of computing (such as Echo Canceller in xDSL Systems) for equalizer design. In order to meet the requirements of system performance and lower cost chips. The research team has designed a lot of high efficiency and low complexity of the equalizer algorithms and architecture. The designs have published several papers in IEEE journals. And these can be used in the design of communications IC design, such as gigabit Ethernet receiver, HDSL, SDSL and SHDSL system.


   In addition, Professor An-Yeu Wu dedicated in teaching courses related to System-on-Chip (SoC) as follows:


1. Editing the "programmable signal processor " experimental materials, and prized for VLSI and system design 'Education Improvement Program works by the Ministry of Education in 1999.

2.Being served as the chief host for SOC Union Ministry of Education in "experimental system chip design" , and editing the "system chip design experimental materials"(with the department of electronics engineering of National Chiao Tung University,and the department of electrical engineering of National Cheng Kung University), rewarded as the "Macronix Young Professor Lecture" in 2003.

3. Giving the first course related to SOC design techniques and experiments,including"Digital System Design"," Introduction to SOC design", and "SOC design experiments", in order to nature talents for the need of incoming SOC era, with basic and advanced design skills.


    In recent years, Professor An-Yeu Wu's research results and teaching have appreciated by domestic and foreign experts, in addition to received "National Science Council reward" four times,"Macronix Young Professors Lecture" in 2003, "Chinese Institute of Engineers project Paper Award"," Golden Silicon Awards for the guidance of Professor," The Chinese Institute of Outstanding Young Electrical Engineers Award ," also he served as many important academic planning and works as following,


  • National Science Council reviewer in the field of Microelectronics.

  • 15th VLSI / CAD Symposium agenda chairman.

  • The main host for SOC Union "system-on-chip design of experiments in the Ministry of Education.

  • Academia Sinica, domestic short-term annual visit to researchers in 2004.

  • ITRI center of the system chip consultant.

  • ITRI Computer and Communications consultant.

  • IA flagship product specifications drafters.

  • Ministry of Economic Affairs Technical Department, "Plan of Industrial Technology Development " review members .

  • Ministry of Economic Affairs Industrial Development Bureau, "Commission of examination of science and technology products or technologies transfer in market," projects reviewer.


  • Associate EditorˇAIEEE Transactions on VLSI Systems

  • Associate EditorˇAEURASIP Journal on Applied Signal Processing   

  • Lead Guest Editor: with the IEEE / IEE Fellow joint planning EURASIP Journal on Applied Signal Processing of the Special Issue on "Signal Processing for Broadband Access Systems: Techniques and Implementations" (in December 2003 edition)
    Panelist: 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

  • Technical Program Committee Member of Major IEEE International Conferences: ICIP, SiPS, AP-ASIC, ISCAS, ISPACS, ICME, APCCAS, and ASIC/SOC. 

        Professor An-Yeu Wu will continue to theoretical innovation, system integration,based on current results, and enhance SOC design techniques as the main objectives in the future research.