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Biography
Research Topics
Research Summarys
Publications
Experience


Journal Papers     Conference Papers

Journal Papers
1.

An-Yeu Wu and K. J. R. Liu, ¡§Split Recursive Least-Squares: Algorithms, Architectures, and Applications,¡¨ IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 43, pp. 645-658, Sept. 1996.-(pdf)
2.

An-Yeu Wu, K. J. R. Liu, and A. Raghupathy, ¡§System Architecture of an Adaptive Reconfigurable DSP Computing Engine,¡¨ IEEE Trans. Circuits and Systems for Video Technology, vol. 8, pp. 54-73, Feb. 1998.-(pdf)
3.

K. J. R. Liu, An-Yeu Wu, A. Raghupathy, and J. Chen, ¡§Algorithm-Based Low-Power and High-Performance Multimedia Signal Processing,¡¨ in Proceedings of the IEEE, Special Issue on ¡§Multimedia Signal Processing¡¨, vol.86, pp. 1155-1202, June 1998.-(pdf)
4. An-Yeu Wu and K. J. R. Liu, ¡§Algorithm-Based Low-Power Transform Coding Architectures: The Multirate Approach,¡¨  IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, pp. 707-718, Dec. 1998.-(pdf)
5. Cheng-Shing Wu and An-Yeu Wu, ¡§Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Architecture,¡¨  IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 48, no. 6, pp. 548-561, June 2001.-(pdf)
6. Tsun-Shan Chan, Jen-Chih Kuo, and An-Yeu Wu, ¡§A Reduced-complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems,¡¨ EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 961-974, Sept. 2002.-(pdf)
7. An-Yeu Wu and Cheng-Shing Wu, ¡§A Unified View for Vector Rotational CORDIC Algorithms and Architectures based on Angle Quantization Approach,¡¨ IEEE Trans. Circuits and Systems Part-I: Fundamental Theory and Applications, vol. 49, no. 10, pp. 1442-1456, Oct. 2002.-(pdf)
8.

Cheng-Shing Wu and An-Yeu Wu, ¡§A Novel Echo Cancellation Algorithm and Architecture Based on Multi-Path Adaptive Interpolated FIR Filter,¡¨ Journal of the Chinese Institute of Electrical Engineering, Part E, vol.10, no.2, pp.135-143, May 2003.-(pdf)
9. Hsin-Chung Wang, Chih-Hsiu Lin, and An-Yeu Wu, Design and Implementation of a Cost-efficient AES Cryptographic Engine¡¨ Journal of NTU Engineering, no. 88, pp. 51-60, June 2003.-(pdf)
10. Huai-Yi Hsu, Sheng-Feng Wang, and An-Yeu Wu, ¡§A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm,¡¨ Special Issue on Signal Processing Systems: Part II, Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 34, no. 3, pp. 251-259, July 2003.-(pdf)
11. Cheng-Shing Wu, An-Yeu Wu, and Chih-Hsiu (Zhi-Xiu) Lin ¡§A High-performance/Low-latency Vector Rotational CORDIC Architecture Based on Extended Elementary Angle Set and Trellis-based Searching Schemes,¡¨ IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 50, no. 9, pp. 589-601, Sept. 2003.-(pdf)
12. Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, and An-Yeu Wu, ¡§VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems,¡¨ Special Issue on ¡§Signal Processing for Broadband Access Systems: Techniques and Implementations, EURASIP Journal on Applied Signal Processing, no. 13, pp. 1306-1316, Dec. 2003.-(pdf)
13. Meng-Da Yang, An-Yeu Wu, and Jyh-Ting Lai, ¡§High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme,¡¨ IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 218-226, Feb. 2004.-(pdf)
14. Meng-Da Yang An-Yeu Wu, and Jyh-Ting Lai, ¡§Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique,¡¨ IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 51, no. 2, pp. 57-60, Feb. 2004.-(pdf)
15. Hung-Yang Ko, Chung-chun Chen, Yi-Chen Wang and An-Yeu Wu,Polar Transmitter for Wireless Communication System,¡¨ Journal of NTU Engineering, no. 93, pp. 39-49, February 2005.-(pdf)
16. Chih-Hsiu Lin and An-Yeu Wu, ¡§Soft-Threshold-based Multi-Layer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture,¡¨ IEEE Trans. Signal Processing, vol. 53, no. 8, pp. 3325-3336, Aug. 2005.-(pdf)
17. Chih-Hsiu Lin and An-Yeu Wu, ¡§Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) Algorithm and Architecture for High-Performance Vector Rotational DSP Applications,¡¨ in IEEE Trans. Circuits and Systems Part-I: Regular Papers, vol. 52, no. 11, pp. 2385-2396, Nov. 2005 (Full paper, SCI, EI). -(pdf)
18. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, ¡§Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Finite-Field Processing Element,¡¨ IEEE Trans. VLSI Systems, vol. 14, no. 5, pp. 489-500, May 2006.-(pdf)
19. Chih-Hsiu Lin, An-Yeu Wu, and Fan-Min Li, ¡§High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems,¡¨ in IEEE Trans. Circuits and Systems, Part-II: Express Briefs, vol. 53, no. 9, pp. 911-915, Sept. 2006.-(pdf)
20. Huai-Yi Hsu, An-Yeu Wu, and Jih-Chiang Yeo, ¡§Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems,¡¨ IEEE Trans. Circuits and Systems, Part-II, vol. 53, no. 11, pp. 1245-1249, Nov. 2006.-(pdf)
21. Jyh-Ting Lai, An-Yeu Wu, and Chien-Hsiung Lee, ¡§Joint AGC-Equalization (Joint AGC-EQ) Algorithm and VLSI Architecture For Wirelined Transceiver Designs,¡¨ IEEE Trans. Very Large Scale Integration (VLSI) Systems (Brief), vol. 15, no.2, pp. 236-240, Feb. 2007.-(pdf)
22. Fan-Min Li, and An-Yeu Wu, ¡§On The New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold,¡¨ IEEE Trans. Signal Processing, vol. 55, no. 11, pp. 5506-5516, Nov. 2007.- (pdf)
23. Jyh-Ting Lai, An-Yeu Wu, and Chien-Hsiung Lee, "A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultra-Wideband Systems," IEEE Trans. Vehicular Technology, vol. 56, no. 6, pp. 3791-3806, Nov. 2007.- (pdf)
24. Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, ¡§An 8.29mm2 52mW Multi-mode LDPC Decoder Design for Mobile WiMAX System in 0.13um CMOS Process ,¡¨ IEEE Jour. Solid-State Circuits, vol. 43, no. 3, pp. 672-683, Mar. 2008.- (pdf)
25. Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, and An-Yeu Wu, "Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme," Journal of Signal Processing Systems (JSPS), vol. 52, no. 1, pp. 59-73, Jul. 2008. - (pdf)
26. Shu-Yen Lin, Chun-Hsiang Huang, Chih-hao Chao, Keng-Hsien Huang, and An-Yeu Wu,"Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks," IEEE Trans. Computers, vol. 52, pp. 1156¡V1168, Sept. 2008. - (pdf)
27. Fan-Min Li, Cheng-Hung Lin, and An-Yeu Wu, ¡§Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel ,¡¨ IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 10, pp. 1358-1371, Oct. 2008.- (pdf)
28. I-Chyn Wey, You-Gang Chen, and An-Yeu Wu, "Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems (Brief), vol. 16, no.12, pp. 1708-1712, Dec. 2008.- (pdf)

Index

Conference Papers
1. An-Yeu Wu and K. J. R. Liu, ¡§A Universal Fast Algorithm and Architecture for Nonstructured RLS Filtering,¡¨ in Proc. Conf. on Information Sciences and Systems., (CISS-93), John Hopkins University, pp.235-240, 1993.-(pdf)
2. K. J. R. Liu and An-Yeu Wu, ¡§A Multi-layer 2-D Adaptive Filtering Architecture based on McClellan Transformation,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-93), Chicago, pp. 1999-2002, 1993.-(pdf) 
3.

 		A.-Y.Wu and K. J. R. Liu, ¡§A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture based on Backward Chebyshev Recursion,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-94), London, pp.4.155-4.158, May 1994.-(pdf) 
4. An-Yeu Wu and K. J. R. Liu, ¡§Algorithm-Based Low-Power Transform Coding Architectures,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-95), Detroit, pp. 3267-3270, May 1995.-(pdf) 
5. An-Yeu Wu, K. J. R. Liu, A. Raghupathy, and S.-C. Liu, ¡§Parallel Programmable Video Co-processor Design,¡¨ in Proc. IEEE Int. Conf. on Image Processing (ICIP-95), Washington D.C., pp. I.61-64, Oct. 1995.-(pdf) 
6. An-Yeu Wu, K. J. R. Liu, Z. Zhang, K. Nakajima, and A. Raghupathy, ¡§Low-Power DSP System Design Using Multirate Approach,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-96), Atlanta, pp.IV.292-295, May 1996.-(pdf) 
7. An-Yeu Wu, and Tsun-Shan Chan, ¡§Cost-efficient Parallel Lattice VLSI Architecture for the IFFT/FFT in DMT Transceiver Technology,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-98), Seattle, pp.VI.3517-3520, May 1998.-(pdf) 
8. An-Yeu Wu, and Kuo-Fuo Hwang, ¡§Optimal Fixed-point VLSI Structure of a Floating-point based Filter Design,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-98), Monterey, pp.V.375-378, May 1998.-(pdf) 
9. An-Yeu Wu, and Cheng-Shing Wu, ¡§Transform-domain Delayed LMS Algorithm and Architecture,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-98), Monterey, pp.V.194-197, May 1998.-(pdf) 
10. An-Yeu Wu, and Tsun-Shan Chan, ¡§Computationally Efficient Fast Algorithm and Architecture for the IFFT/FFT in DMT/OFDM Systems,¡¨ in IEEE Workshop on Signal Processing Systems (SiPS-98), Boston, pp.356-365, Oct. 1998.-(pdf) 
11. An-Yeu Wu,, Tsun-Shan Chan, and Bowen Wang, ¡§A Fast Algorithm for Reduced-complexity Programmable DSP Implementation of the IFFT/FFT in DMT Systems,¡¨ in IEEE 1998 Global Telecommunications Conference (GLOBECOM-98), Sydney, pp. 471-476, Nov. 1998.-(pdf) 
12. Cheng-Shing Wu and An-Yeu Wu, ¡§A Novel Multirate Adaptive FIR Filtering Algorithm and Architecture,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-99), Phoenix, pp.IV.1849-1852, March 1999.-(pdf) 
13. Jye-Jong Leu and An-Yeu Wu, ¡§A Scalable Low-Complexity Digit-Serial VLSI Architecture for RSA Cryptosystem,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-99), Taipei, pp. 586-595, IEEE Press, Oct. 1999.-(pdf) 
14. Cheng-Shing Wu and An-Yeu Wu, ¡§Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Its Application to FFT,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2000), Geneva, pp.IV.529-532, May 2000.-(pdf) 
15. Jye-Jong Leu and An-Yeu Wu, ¡§Design Methodology for Booth-encoded Montgomery Module Design for RSA Cryptosystem,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2000), Geneva, pp. V.357-360, May 2000.-(pdf) 
16. Cheng-Shing Wu and An-Yeu Wu, ¡§A Novel Rotational VLSI Architecture Based on Extended Elementary Angle Set CORDIC Algorithm,¡¨ in Proc. IEEE Asia Pacific Conf. on ASICs (AP-ASIC 2000), Cheju, Korea, pp.111-114, Aug. 2000.-(pdf) 
17. Chi-li Yu and An-Yeu Wu, ¡§An Improved Time-Recursive Lattice Structure for Low-Latency IFFT Architecture in DMT Transmitter,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2001), Sydney, vol. 4, pp. 250-253, May 2001.-(pdf) 
18. Cheng-Shing Wu and An-Yeu Wu, ¡§A Novel Trellis-based Searching Scheme for EEAS-based CORDIC Algorithm,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), Salt Lake City, vol. 2, pp. 1229-1232, May 2001.-(pdf) 
19. An-Yeu Wu and Cheng-Shing Wu, ¡§A Unified Design Framework for Vector Rotational CORDIC Family Based on Angle Quantization Process,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), Salt Lake City, vol. 2, pp. 1233-1236, May 2001.-(pdf) 
20. I-Hsien Lee, Ceng-Shing Wu, and An-Yeu Wu, ¡§Cost-Efficient Multiplier-less FIR Filter Structure Based on Modified DECOR Transformation,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), Salt Lake City, vol. 2, pp. 1065-1068, May 2001.-(pdf) 
21. Chih-Chi Wang and An-Yeu Wu, ¡§A Cost-effective TEQ Algorithm for ADSL Systems,¡¨ in Proc. IEEE International Conf. on Communications (ICC-2001), Helsinki, Finland, vol. 2, pp. 398-402, June 2001.-(pdf) 
22. Sheng-Feng Wang, Huai-Yi Hsu, and An-Yeu Wu, ¡§A Very Low-Cost Multi-mode Reed Solomon Decoder based on Peterson-Gorenstein-Zierler Algorithm,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2001), Antwerp, Belgium, pp. 37-48, Sept. 2001.-(pdf) 
23. Cheng-Shing Wu and An-Yeu Wu, ¡§A Novel Cost-Effective Multi-path Adaptive Interpolated FIR (IFIR)-Based Echo Canceller,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2002), Phoenix, vol. 5, pp. 453-456, May 2002.-(pdf) 
24. Meng-Da Yang and An-Yeu Wu, ¡§A New Pipelined Adaptive DFE Architecture with Improved Convergence Rate,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2002), Phoenix, vol. 4, pp. 213-216, May 2002.-(pdf) 
25. Huai-Yi Hsu and An-Yeu Wu, ¡§VLSI Design of A Reconfigurable Multi-mode Reed-Solomon Codec for High-Speed Communication Systems,¡¨ in Proc. IEEE Asia Pacific Conf. on ASICs (AP-ASIC 2002), Taipei, ROC, pp. 359-362, Aug. 2002.-(pdf) 
26. Meng-Da Yang and An-Yeu Wu, ¡§High-performance Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer Scheme,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2002), San Diego, USA, pp. 121-126, Oct. 2002.-(pdf) 
27. Zhi-Xiu Lin and An-Yeu Wu, ¡§Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) Algorithm and Architecture for Scaling-Free High-Performance Rotational Operations,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2003), Hong Kong, vol. II, pp. 653-656, April 2003.-(pdf) 
28. An-Yeu Wu, I-Hsien Lee, and Cheng-Shing Wu, ¡§Angle Quantization Approach for Lattice IIR Filter Implementation and Its Trellis De-Allocation Algorithm,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2003), Hong Kong, vol. II, pp. 673-676, April 2003.-(pdf) 
29. Jen-Chih Kuo, Ching-Hua Wen, and An-Yeu Wu, ¡§Implementation of a Programmable 64~2048-Point FFT/IFFT Processor for OFDM-based Communication Systems,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2003), Bangkok, vol. II, pp. 121-124, May 2003.-(pdf) 
30. Jyh-Ting Lai, An-Yeu Wu, and Cheng-Chung Yeh, ¡§A Novel Multipath Matrix Algorithm for Exact Room Response Identification in Stereo Echo Cancellation,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2003), Seoul, Korea, pp. 236-240, Aug. 2003.-(pdf) 
31. Pen-Hsin Chen, Kai-Huang, Nai-Hsuan Hsueh, and An-Yeu Wu, ¡§Dual-Mode Convolutional/SOVA Based Turbo Code Decoder VLSI Design for Wireless Communication Systems,¡¨ in Proc. IEEE International SOC Conference (formerly IEEE International ASIC/SOC Conference), Portland, pp. 369-372, Sept. 2003.-(pdf) 
32. Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, and An-Yeu Wu, ¡§Least Squares Approximation-based ROM-free Direct Digital Frequency Synthesizer,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), Vancouver, vol. II, pp. 701-704, May 2004.-(pdf) 
33. Kai Huang, Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, ¡§VLSI Design of Dual-mode Viterbi/Turbo Decoder for 3GPP,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), Vancouver, vol. II, pp. 773-776, May 2004.-(pdf) 
34. Hsiu-ping Lin, Nancy F. Chen, Jyh-Ting Lai, and An-Yeu Wu, ¡§1000BASE-T Gigabit Ethernet Baseband DSP IC Design,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), Vancouver, vol. IV, pp. 401-404, May 2004.-(pdf) 
35. Kai-Yuan Jheng, Shyh-Jye Jou, and An-Yeu Wu, ¡§A Design Flow for Multiplierless Linear-phase FIR Filters: From System Specifications to Verilog Code,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), Vancouver, vol. V, pp. 293-296, May 2004.-(pdf) 
36. I-Chyn Wey, Hwang-Cherng Chow, You-Gang Chen, and An-Yeu Wu, ¡§A Fast and Power-Saving Self-Timed Manchester Carry-Bypass Adder for Booth Multiplier-Accumulator Design,¡¨ in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Fukuoka, Japan, pp. 50-53, Aug. 2004.-(pdf) 
37. Shyh-Jye Jou, Kai-Yuan Jheng, Hsiao-Yun Chen, An-Yeu Wu, ¡§Multiplierless Multirate Decimator/Interpolator Module Generator,¡¨ in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Fukuoka, Japan, pp. 58-61, Aug. 2004.-(pdf) 
38. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, ¡§Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems,¡¨ in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Fukuoka, Japan, pp. 314-317, Aug. 2004.-(pdf)
39. Chih-Hsiu Lin and An-Yeu Wu, ¡§Robust Decision Feedback Equalizer Design using Soft-Threshold-based Multi-layer Detection Scheme,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), Austin, USA, pp. 118-123, Oct. 2004.-(pdf) 
40. Jih-Chiang Yeo, Huai-Yi Hsu, and An-Yeu Wu, ¡§A Scalable Reed-Solomon Decoding Processor based on Unified Finite-field Processing Element Design,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), Austin, USA, pp. 148-151, Oct. 2004.-(pdf) 
41. Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, ¡§'Triple-Mode MAP/VA Timing Analysis for Unified Convolutional/Turbo Decoder Design,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), Austin, USA, pp. 280-285, Oct. 2004.-(pdf) 
42. Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, ¡§Unified Convolutional/Turbo Decoder Architecture Design Based on Triple-Mode MAP/VA Kernel,¡¨ in Proc. IEEE Asia-Pacific Conf. Circuits and Systems (APCCAS 2004), Tainan, Taiwan, vol.2, pp. 1073-1076, Dec. 2004.-(pdf) 
43. Chih-Hsiu Lin and An-Yeu Wu, ¡§Low-Cost Decision Feedback Equalizer (DFE) Design for Giga-Bit Systems,¡¨ in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2005), Philadelphia, USA, vol. 3, pp. 1001-1004, March 2005.-(pdf) 
44. Kai-Yuan Jheng, Tsung-Han Wu, Yi-Chiuan Wang, Jih-Chiang Yeo, Yu-Ju Cho, and An-Yeu Wu, ¡§A DVB-T Baseband Demodulator Design Based on Multimode Silicon IPs A DVB-T Baseband Demodulator Design based on Multimode Silicon IPs,¡¨ in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2005), Hsinchu, TAIWAN, pp. 49-52, April 2005.-(pdf) 
45. Tsung-Han Tsai, Cheng-Hung Lin, and An-Yeu Wu, ¡§A Memory-Reduced Log-Map Kernel For Turbo Decoder,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), Kobe, JAPAN, pp. 1032-1035, May 2005.-(pdf) 
46. I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, and An-Yeu Wu, ¡§A 2Gb/S High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for Soc Applications,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), Kobe, JAPAN, pp. 1074-1077, May 2005.-(pdf) 
47. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu Wu, ¡§A Scalable DCO Design for Portable ADPLL Designs,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), Kobe, JAPAN, pp. 5449-5452, May 2005.-(pdf) 
48. Hung-Yang Ko, Yi-Chiuan Wang, and An-Yeu Wu, ¡§Digital Signal Processing Engine Design For Polar Transmitter,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), Kobe, JAPAN, pp. 6026-6029, May 2005.-(pdf) 
49. Cheng-Hung Lin, Fan-Min Li, Xin-Yu Shi, and An-Yeu Wu, ¡§A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems,¡¨ in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2005), Hsinchu, TAIWAN, pp. 221-224, Nov. 2005.-(pdf) 
50. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, ¡§Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design,¡¨in Proc. Student Design Contest of IEEE Asian Solid-State Circuits Conf. (A-SSCC-2005), Hsinchu, TAIWAN, pp. 533-536, Nov. 2005.-(pdf) 
51. Fan-Min Li, and An-Yeu Wu, ¡§A New Stopping Criterion for Efficient Early Termination in Turbo Decoder Designs,¡¨ in Proc. 2005 Int. Symp. Intelligent Signal Processing and Communication Systems (ISPACS-2005), Hong Kong, CHINA, pp. 585-588, Dec. 2005.-(pdf) 
52. Chung-Chun Chen, Hung-Yang Ko, Yi-Chiuan Wang, Hen-Wai Tsao, Kai-Yuan Jheng, and An-Yeu Wu, ¡§Polar Transmitter for Wireless Communication System,¡¨ in Proc. 2005 Int. Symp. Intelligent Signal Processing and Communication Systems (ISPACS-2005), Hong Kong, CHINA, pp. 613-616, Dec. 2005.-(pdf)
53. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, and An-Yeu Wu, ¡§A Portable All-Digital Pulsewidth Control Loop for SOC Applications,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), Island of Kos, GREECE, pp. 3165-3168, May 2006.-(pdf)
54. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu Wu, ¡§A Frequency Estimation Algorithm for ADPLL Designs with Two-cycle Lock-in Time,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), Island of Kos, GREECE, pp. 4082-4085, May 2006.-(pdf)
55. Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, and Hen-Wai Tsao, ¡§DSP Engine Design for LINC Wireless Transmitter Systems,¡¨ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), Island of Kos, GREECE, pp. 2593-2596, May 2006.-(pdf)
56. Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, and An-Yeu Wu, ¡§Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, CANADA, pp. 62-65, Oct. 2006.-(pdf)
57. Fan-Min Li, Cheng-Hung Lin, and An-Yeu Wu, ¡§A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, CANADA, pp. 89-94, Oct. 2006.-(pdf)
58. Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, and Wen-Chiang Chen, ¡§A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-WideBand Systems,¡¨in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, Canada, pp. 165-170, Oct. 2006.-(pdf)
59. Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, and Wen-Chiang Chen, ¡§A Low Cost Packet Detector in OFDM-based Ultra-WideBand systems,¡¨in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, CANADA, pp. 171-176, Oct. 2006.-(pdf)
60.

Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, and An-Yeu Wu, ¡§A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10Gbase-T Ethernet System,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, CANADA, pp. 330-333, Oct. 2006.-(pdf)
61. Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, and An-Yeu Wu, ¡§On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems,¡¨ in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), Banff, CANADA, pp. 426-431, Oct. 2006.-(pdf)
62. I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu Wu, ¡§A 0.18£gm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement,¡¨ in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2006), Hangzhou, CHINA, pp. 291-294, Nov. 2006.-(pdf)
63. You-Gang Chen, I-Chyn Wey, and An-Yeu Wu, ¡§A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment,¡¨ in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2006), Hangzhou, CHINA, pp. 295-298, Nov. 2006.-(pdf)
64. Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao, and Bosen Tzeng, ¡§Multilevel LINC System Design for Wireless Transmitters,¡¨ in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2007), Hsinchu, TAIWAN, pp.208 - 211, April, 2007.-(pdf)
65. Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, and An-Yeu Wu, ¡§A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network,¡¨ in Proc. ACM/IEEE Int. Symp. Networks-on-Chip (NOCS-2007), Princeton, USA, pp. 317-322, May 2007.-(pdf)
66. Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, and An-Yeu Wu, "Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), New Orleans, USA, pp. 869-872, May 2007.-(pdf)
67. Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, and Weber Chien, "A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), New Orleans, USA, pp. 869-872, May 2007.-(pdf)
68. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu and Hong Zhao, "Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), New Orleans, USA, pp. 1803-1806, May 2007.-(pdf)
69. Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, "A 19-mode 8.29mm2 52-mW LDPC Decoder Chip for IEEE 802.16e System," in Proc. Int. Symp. VLSI Circuits (SOVC-2007), Kyoto, JAPAN, pp. 16-17, June 2007.-(pdf)
70. Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu Wu, "Multilevel LINC System Design For Power Efficiency Enhancement," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), Shanghai, China, pp. 31-34, Oct. 2007.-(pdf)
71. Tzu-Hao Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, and An-Yeu Wu, "Reconfigurable Color Doppler DSP Engine For High - Frequency Ultrasonic Image Systems," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007) , Shanghai, China, pp. 187-192, Oct. 2007.-(pdf)
72. Chun-Yuan Chu, Jyh-Ting Lai, and An-Yeu Wu, "Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based UWB systems," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), Shanghai, China, pp. 403-406, Oct. 2007.-(pdf)
73. Chi-Li Yu, Tzu-Hao Yu, and An-Yeu Wu, "On The Fixed-Point Properties of Mixed-Scalling-Rotation CORDIC Algorithm," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007) , Shanghai, China, pp. 430-435, Oct. 2007.-(pdf)
74. Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, and An-Yeu Wu, "Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), Shanghai, China, pp. 493-498, Oct. 2007.-(pdf)
75. I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu Wu, " A 0.13£gm Hardware-Efficient Probabilistic-Based Noise-Tolerant Circuit Design and Implementation with 24.5dB Noise-Immunity Improvement," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2007), Jeju, Korea, pp. 295-298, Nov. 2007.-(pdf)
76. Cheng-Zhou Zhan, Xin-Yu Shih, and An-Yeu Wu, ¡§High-Performance Scheduling Algorithm for Partially Parallel LDPC Decoder,¡¨ in Proc. IEEE Int. Conf. Acoustic, Speech, Signal Processing (ICASSP-2008), Las Vegas, USA, pp. 3177-3178, Mar., 2008.-(pdf)
77. Cheng-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, ¡§High-Throughput 12-Mode CTC Decoder for WiMAX Standard,¡¨in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), Hsinchu, Taiwan, pp.216-219, April, 2008.-(pdf)
78. Chun-Yuan Chu, Yu-Chuan Huang, and An-Yeu Wu, ¡§Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder,¡¨in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), Hsinchu, Taiwan, pp.228-231, April, 2008.-(pdf)
79. Yen-Liang Chen, Chun-Yu Chen, Kai-Yuan Jheng, and An-Yeu Wu, ¡§A Universal Look-Ahead Algorithm for Pipelining IIR Filters,¡¨ in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), Hsinchu, Taiwan, pp.259-262, April, 2008.-(pdf)
80. Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, and An-Yeu Wu, "Overview of ITRI PAC Project ¡V from VLIW DSP Processor to Multicore Computing Platform," in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), Hsinchu, Taiwan, pp. 188-191, April, 2008. (invited)-(pdf)
81. Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey and An-Yeu Wu,"An Efficient Methodology to Evaluate Nanoscale Circuit Fault-tolerance Performance based on Belief Propagation," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008), Seattle, USA, pp. 608-611, May, 2008.-(pdf)
82. Cheng-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, ¡§Low-Power Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder,¡§ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008), Seattle, USA, pp. 736-739, May, 2008.-(pdf)
83. Yen-Liang Chen, Cheng-Zhou Zhan, and An-Yeu Wu, ¡§Cost-Effective Echo and Next Canceller Designs for 10GBASE-T Ethernet System,¡§ in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008), Seattle, USA, pp. 3150-3153, May, 2008.-(pdf)
84. Chih-Hao Chao, Chun-Yuan Chu and An-Yeu Wu, "Location-Constrained Particle Filter for RSSI-Based Indoor Human Positioning and Tracking System," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), DC, USA, pp. 73-76, Oct. 2008.-(pdf)
85. Chun-Yu Chen, Cheng-Hung Lin and An-Yeu Wu, "High-Throughput Dual-Mode Single/Double Binary Map Processor Design for Wireless WAN," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), DC, USA, pp. 83-87, Oct. 2008.-(pdf)
86. Ting-Jung Lin, Shu-Yen Lin and An-Yeu Wu, "Traffic-Balanced IP Mapping Algorithm for 2D-MESH On-Chip-Networks," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), DC, USA, pp. 200-203, Oct. 2008.-(pdf)
87. Xin-Yu Shih, Cheng-Zhou Zhan, and An-Yeu (Andy) Wu, "A 7.39mm2 76mW (1944, 972) LDPC Decoder Chip for IEEE 802.11n Applications,¡¨ in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2008), Fukuoka, JAPAN, pp. 301-304, Nov. 2008 .-(pdf)

Index

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